Intel Setting the Stage
RISC and reward
This is the fourth entry in a multipart series. You may be interested to read about Shockley Semiconductor, Fairchild Semiconductor, the start of Intel, the rise of the 8086, and the failure of the 432 and success of the 386.
Until the launch of the i386, Intel had had several second sources for its chips. In the early semiconductor industry, second sources were often required for large companies to be willing to buy in volume. Manufacturing was difficult, and buyers wanted to be assured that they could continue to get the chips for their products should the semiconductor manufacturer in question run into trouble. The importance of this could be seen in the failures of Shockley and Fairchild. For Intel, their second source partners included AMD, Fujitsu, Harris, IBM, Intersil, MME, and Siemens among others. Yet, as I noted, this was the situation until the i386, and Intel really didn’t want to share the market for the i386.
AMD had begun official second sourcing of Intel’s products with a 1976 patent exchange agreement. This was followed by another agreement announced in October of 1981, taking effect in 1982, and extending until 1992. Intel had created this agreement with AMD due to demands by IBM that Intel have a domestic second source for the 8086/8088 as prior to this Intel’s second sources were Fujitsu and Siemens. This agreement was amended in 1984 and allowed AMD to be a second source for the 80186 and 80286 microprocessors.
IBM, in the middle of the 1980s, had little interest in the i386 as Big Blue was trying to take all of their semiconductor manufacturing in-house, and Intel already had a major customer in Compaq (among other IBM-compatible manufacturers) who wasn’t too worried about having a second source. These two facts gave Intel some freedom, but there was the agreement with AMD to consider. This agreement was partially contingent on the two companies having products of more or less equal value to exchange with one another, and Intel claimed that AMD had nothing to offer them. No doubt the company’s executives and legal staff felt assured in their legal rights with this matter due to a ruling by Judge William Ingram in September of 1986 in Intel’s case against NEC that microcode could be covered by copyright, and the i386 made extensive use of microcode. Thus, while the patents may have needed to have been exchanged, the copyrights, and thereby microcode, wouldn’t.
A more salient reason for this change in behavior was just how bad 1985 and 1986 were for Intel financially. The company had closed 1985 with just $1.5 million in income, and for 1986, the company posted a loss of $173,165,000. That loss combined with the company’s recent closures of smaller and outdated manufacturing facilities, the shift from memories to processors, and increased competition from companies overseas resulted in a staff reduction of 7200 people. If we combine the poor financial position of the company at this time with the, as Andy Grove referred to it, unprecedented enthusiasm for the i386, we can see that Intel was seeing a huge profit potential that it indisputably needed.
There were two major events in 1987 at Intel. The first, Andy Grove took over as CEO, and his particular style would fundamentally change Intel. Grove’s early nervousness with leaving Fairchild for a startup had matured into a healthy distrust of seeming success that is best captured in his own words:
Business success contains the seeds of its own destruction. Success breeds complacency. Complacency breeds failure. Only the paranoid survive.
The response to this distrust of success was captured in another statement by Grove:
A corporation is a living organism; it has to continue to shed its skin. Methods have to change. Focus has to change. Values have to change. The sum total of those changes is transformation.
In a practical sense, this meant that Intel’s employees had some new freedom to develop and test new ideas, products, sales channels, and so on. With this came Grove’s belief that knowledge was more important than title. He worked out of a standard cubicle as did so many employees, and he was rather humble and modest in most parts of his life. Grove brought a strong sense of egalitarianism to Intel, but this wasn’t complete freedom; Grove also believed that the most powerful word an executive could use was no.
The second major event was AMD exercising the arbitration clause in their patent cross-licensing contract in April. Intel then responded by terminating the second source agreement from 1982 with a year’s notice. The legal battle would continue for quite some time.
Otherwise, demand for the i286 and i386 increased, Intel finally met demand for the i286, and production for the i386 was expected to triple in 1988. Intel closed the year with income of $248,055,000 on revenues of $1,907,105,000.
1988 was a year of recovery for Intel. They introduced the 82526 CAN bus controller for automobiles in February, and 16 other products were announced on the 5th of April at the Santa Clara Convention Center among which were the i960 and flash memory.
The i960 was Intel’s first RISC chip. It had a large register set, most instructions were completed in a single cycle, and it was pipelined. Or, that’s kind of how it is. There were four different architecture SKUs of the i960. The first was the Core (80960KA) that was the RISC chip. Next was the Numerics (80960KB) architecture that added floating point. Then came the Protected (80960MC) architecture that added paged memory management, supervisor/user protection, strings, scheduling, interprocess communication for the OS, and symmetric multiprocessing. Finally was the Extended (80960XA) architecture which added object addressing and protection, and interprocess communication for applications. Things got weirder though as these four chips were physically identical. They were exactly the same die but each had various parts disabled simply by not having pins attached in the package. So, in the KA, all of the needed parts were there for the chip to be an XA, but pins were only connected along one side of the chip.
Intel took 200th place in the Fortune 500 closing 1988 with income of $452,922,000 on revenues of $2,874,769,000.
The N10 project had been led by Leslie “Mr. RISC” Kohn, and the requirements for the chip had been gathered via discussions with potential customers in the supercomputer, workstation, and minicomputer markets. Meeting the needs of these customers was a tall order, and Intel wouldn’t lack competition in those markets with SGI, Sun, and Motorola largely having taken them entirely. This was all leading to quite an ambitious design. The final decision had rested with Albert Yu (VP of Component Technology and Development) on whether or not to proceed, and he said of his decision “A lot depends on gut feel. You take chances at these things.” With his decision to move forward, real development had begun in January of 1986. Kohn was having to compete with the i486 team for resources, computer time, and staff, so he chose to keep his team small and nimble. To manage the team with Kohn, Yu brought in Sai Wai Fu who’d been a classmate of Kohn’s at CalTech. In the end, the team consisted of 20 engineers. This was more than Kohn and Fu had initially thought they’d need, but it was a considerably smaller team than that of the i486.
Given the market segments already mentioned, Kohn wanted a RISC core that had high performance integer and floating point, vector operations, large caches, single cycle multiple instruction execution, pipelining, a 64bit databus, and a 128bit bus between cache and the FPU.
When Fu made the first sketch, he realized that they’d need to cut their cache segments from four to two given their size constraints, and many more things were adjusted over time. The primary driving goal for the project was that every instruction should be completed in a single clock cycle, but this wouldn’t hold for every single operation. For example, rather than optimizing floating-point division, the team opted for IEEE standards as customers apparently preferred conformity. The dogma for the design team was to avoid creeping elegance. This stressed not taking unnecessary risks, adhering to established methodologies, and ensuring that each constituent component on the chip would output signals that integrated with the rest.
The parallel execution was somewhat unique at the time. The instruction cache had two 32bit segments. These would be issued simultaneously with one to the RISC core and the other to the floating point unit. This resulted in two instructions per clock with some regularity, but occasionally would provide three as some floating point instructions would call the adder and multiplier concurrently.
On the 27th of February in 1989, Intel introduced the N10 as the 80860, better known as the i860. The i860 was built of one million transistors and could be clocked from 25MHz to 40MHz. It supported core instructions which made use of a 32bit ALU, and floating point or graphics instructions that used either the floating point adder, multiplier, or graphics unit. These two instruction types could be executed simultaneously, and the chip achieved its goal of two to three instructions per clock being regularly achievable. Data sizes could range from 8bits to 128bits, and the graphics operations present on the i860 gave Intel the experience needed to later create MMX. While the i860 was ambitious and in its best case scenarios could offer peak performance as high as 80MFLOPS, real world performance was closer to 10 to 40MFLOPS. A major factor in this was a rather high context switching penalty due to having multiple pipelines. As compilers were better optimized, many of the architecture’s inefficiencies were remedied, but by the time this happened, the i860 wasn’t a leading edge competitor. The chip was used in some supercomputers, some workstations, and even as an accelerator in some i486 machines, but it wasn’t a major commercial success. One area where the i860 did reasonably well was in military applications as a DSP. Its legacy is more acutely felt in the expertise it built within Intel, and in the naming of Windows NT. While VMS incremented becomes WNT, N10 is also a source of the name as Windows NT was developed on the i860 early in its life. On a final note, the i860 is often cited as a VLIW chip, and I do not agree with this designation (despite having written that it was such myself in the linked article there). It is similar in some respects, but a VLIW chip executes many instructions per clock explicitly, and in the case of the i860 these cannot be the same instruction type. Thus, i860 was more accurately a RISC chip with an accelerator on-die whose instructions were executed in a VLIW-like manner. This is a somewhat pedantic quibble, but one that can more accurately describe the i860. It was a unique chip with some awesome ideas, and it deserves to be recognized on its own merits.
On the 10th of April in 1989 at COMDEX, Intel introduced the 80486, or i486. John Crawford and Pat Gelsinger had started work on this processor shortly after the release of the i386. They’d finished the logic and microcode in 1988, and tapeout was completed on the 1st of March in 1989 with first silicon arriving on the 20th of March in 1989. The primary differences between the i386 and the i486 are that the i486 includes an 8K on-chip L1 cache, an improved bus protocol, improved pipelining, an integrated FPU, doubled prefetch queue, higher performance MMU, and a few more instructions. The i486 was on the market until the 28th of September in 2007, and thus ranges from 16MHz to 100MHz, has caches ranging from 8K to 16K, and could be found on process nodes from 1 micron to 600nm. The transistor count of the first models was 1.2 million, but later models bumped this to 1.6 million. The Intel 80486 was roughly 50 times more powerful than the 8088 (with surrounding improvements factored in); that is, the IBM-compatible PCs that shipped later in the year with an i486 were the equivalent of 50 original 5150s in compute power. This was achieved in slightly less than 9 years time. The world was changing quickly thanks to Intel’s work.
On the 12th of September in 1989, Intel announced the 80960CA. This was an evolution of the i960, but it was also superscalar. The i960CA had three execution units that could operate in parallel, and these were fed by an instruction sequencer that examined four instructions at a time determining which of these could be executed simultaneously. Ultimately, the chip could handle two instructions and a branch each clock cycle, and this chip used branch prediction to enable speculative execution. The i960CA was clocked at 33MHz, was capable of 66MIPS, lacked the FPU and MMU of prior chips in the series, and it was targeted at high performance embedded applications.
For 1989, Intel posted income of $391,021,000 on revenues of $3,126,833,000. Across Intel’s various product lines, one can easily see what is to come. Combining these with Windows 2’s 386 version, the software that would accompany these future Intel products is also apparent. While many companies would fall on hard times in that coming decade, computers would find their way into the homes of people all over the globe in numbers never before seen.
I have readers from many of the companies whose history I cover, and many of you were present for time periods I cover. A few of you are mentioned by name in my articles. All corrections to the record are welcome; feel free to leave a comment.